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- Bumping
Wafer Bumping
Wafer Bumping is an advanced wafer level packaging technology which uses solder bumps to form the interconnection between the integrated circuit (IC) and the package, and it is a replacement of wire bonding technology. This technology has the benefit of high density, good thermal dissipation and good electrical performance. SPIL provides customers with both 200mm and 300mm wafer bumping services, including printed bump, plated bump and ball placement technology with eutectic, lead free and copper pillar materials.
APPLICATIONS
| Solder Bump | Ball Placement | Cu pillar bump | µbump | |
|---|---|---|---|---|
| Application | Graphic / GPU / APU | PMIC | AP | HPC/Network |
| Chipset | Wireless | PMIC | Server AI | |
| Wireless | Audio | Graphic / GPU / APU / AP / AI | IoT / Wearable | |
| FPGA | RF | Chipset | ||
| Storage | Amplifie | Wireless | ||
| ASIC / PMIC | Pre-Amp | FPGA | ||
| RFIC | ASIC | |||
| RFIC |
PROCESS CAPABILITY
| Solder Bump | Ball Placement | Cu pillar bump | µbump | |
|---|---|---|---|---|
| Wafer size | 12 inch / 8 inch | 12 inch / 8 inch | 12 inch / 8 inch | 12 inch / 8 inch |
| Process | 1. FOC 2. REPSV 3. RDL |
1. REPSV 2. RDL |
1. FOC 3. RDL |
1. FOC ( uBump) 2. uPad + TSV reveal + C4 bump |
| Min. bump pitch | Array: 150um | Array: 300um | Array: 60um | Array: 40um |
| Bump material | 1. Sn/Ag 2. SnAgCu |
SnAgCu | 1. Cu/NI/SnAg 2. Cu/SnAg |
Cu/NI/Cu/SnAg (uBump) Cu/SnAg ( C4) |
| RDL trace | Cu | Cu | Cu | Cu |
| Bump/Ball height | Target ± 10% Coplanarity < 20 um |
Target ± 15 um Coplanarity < 30 um |
Target ± 10% Coplanarity < 20% |
Target ± 10% Coplanarity < 20% |
| Bump/Ball Diameter | Target ± 10% | Target ± 10% | Target ± 10% | Target ± 10% |
| Bump/Ball shear force | Pb-free Bump : >2.5 g/mil² | Pb-free Bump : >2.5 g/mil² | Solder tip >2.5 g/mil² Cu pillar : >7 g/mil² |
Solder tip >2.5 g/mil² Cu pillar : >7 g/mil² Pb-free Bump : >2.5 g/mil² |
